Programmable logic arrays are commonly used in digital design to achieve a specific logical operation by interconnecting a generic conductor structure in a predetermined manner. One conventional PLA structure comprises first and second planes of conductors commonly referred to as the AND-plane and the OR-plane. The AND-plane includes first row conductors coupled for receiving the input signals and column conductors connected to the first row conductors at predetermined intersections. The OR-plane uses the same column conductors interconnected with second row conductors for providing the output signals of the PLA with the specified logic function. The column conductors are typically positioned perpendicular to the first and second row conductors with a transistor disposed at each intersection thereof such that the gate and drain terminals of those transistors needed to achieve the desired logical operation of the PLA are coupled to appropriate row and column conductors.
The column conductors and second row conductors each have an active pull-up circuit responsive to first and second clock signals operating at different frequencies to pre-charge the conductors at the start of each PLA processing cycle. The first and second clock signals are ideally in-phase, with the first clock signal operating at say four megahertz while the second clock signal operates at two megahertz. The first and second clock signals establish multiple time slots for processing the input signal through the PLA while avoiding any DC conduction paths between the positive power supply conductor through the active pull-up transistors to ground potential. Such DC conduction paths can cause unacceptable static power drain through the PLA.
During a first time slot of the PLA processing cycle when both the first and second clock signals are high, the active pull-up devices pre-charge the column conductors of the AND-plane and second row conductors of OR-plane to a logic one. Each of the transistors interconnecting the AND-plane and OR-plane have their sources coupled to a virtual ground which is disabled during the first time slot preventing the input signals from pulling the column conductors of the AND-plane to logic zero at the same time the active pull-up transistors are conducting thereby avoiding the DC conduction paths. During a second time slot when the first clock signal is low and the second clock signal is still high, the active pull-up transistors are disabled and the virtual ground is re-enabled allowing the logic levels of the input signals to pull the associated column conductors to logic zero while the remaining conductors (not pulled low) maintain the pre-charged logic high. During a third time slot when the second clock signal becomes low, the logic levels on the column conductors of the AND-plane are transferred to the second row conductors of the OR-plane and out the PLA.
The virtual ground for the interconnecting transistors between the AND-plane and the OR-plane is typically provided at the interconnecting node between two N-channel MOS transistors serially coupled between the positive power supply conductor and ground potential. The virtual ground is enabled when the lower transistor is conducting and disabled when the upper N-channel device is conducting pulling the interconnecting node of the transistors to logic high. Unfortunately, the virtual ground concept has several drawbacks. The N-channel transistors providing the virtual ground are typically disposed on diffusion layers which are often widened to keep the resistance low and ensure adequate ground. However, widening the diffusion layer also increases the capacitance which slows downs the propagation of the input signals. Moreover, the active pull-up transistors must also charge the larger diffusion capacitance which contributes to the slower operation of the PLA and causes higher switching currents.
Another significant problem with the conventional PLA circuit is the use of first and second clock signals operating at different frequencies to generate the time slots for precharging the conductors and processing the input signals through the PLA. Great care must be taken to ensure the edges of the first and second clock signals are aligned to avoid generating unwanted pulses which may, for example, enable the active pull-up transistors during the second time slot when the input signal is processing through the PLA and thereby create glitches in the output signals. The first and second clock signals are highly susceptible to timing skew between their transitions since they are often generated external to the PLA and may travel considerable distance through one or more integrated circuits of the system before reaching the PLA. It is necessary to carefully analyze the phasing of the first and second clock signals and compensate for any timing skew therebetween at the input of the PLA.
Hence, what is needed is an improved PLA circuit operating without the special multiple clocking schemes in order to avoid the timing skew problem. Furthermore, it is desirable to eliminate the virtual grounds for the interconnecting transistors between the row and column conductors.